Custom 24-bit CPU
A processor designed from scratch in Verilog: my own instruction encoding, my own 11-state control unit, no provided skeleton.
Every student in the class received a personalised specification, so there was no shared solution to converge on and nothing to copy. You get a set of constraints and you go design a computer.
Mine is a 28-bit instruction encoding with a 4-bit opcode over eight instructions and a 12-bit immediate field, running on a multi-cycle datapath driven by an eleven-state finite state machine: fetch, decode, two execute states, memory address, memory read, memory write, three writeback states, and branch.
Memory is Von Neumann, a single 16,384-location address space shared between instructions and data over a 14-bit bus, with programs loaded at 0x2000 and PC-relative branching. Verified through RTL simulation and synthesis running both an arithmetic program and a counted loop.
What it does
- Designed a custom 28-bit instruction set architecture: 4-bit opcode over 8 instructions (ADD, SUB, ADDI, LW, SW, BEQ, AND, SLT) and a 12-bit immediate field.
- Implemented the full multi-cycle datapath in Verilog: an 11-state control FSM, ALU with 2-bit control, 16×24 register file, instruction decode, and memory interface.
- Von Neumann memory organization addressing 16,384 locations over a 14-bit bus, with PC-relative branching from a fixed 0x2000 entry point.
- Verified through RTL simulation and synthesis, running an arithmetic program and a counted loop to completion.
Built with
- Verilog
- RTL simulation
- Synthesis
- ISA design
- Testbenches